WO2025177136 - QUANTUM PROCESSOR ARCHITECTURE
National phase entry is expected:
Publication Number
WO/2025/177136
Publication Date
28.08.2025
International Application No.
PCT/IB2025/051691
International Filing Date
17.02.2025
Title **
[English]
QUANTUM PROCESSOR ARCHITECTURE
[French]
ARCHITECTURE DE PROCESSEUR QUANTIQUE
Applicants **
STERN, Michael
Inventors
GINOSSAR, Eran
LUPO, Elena
Priority Data
63/555,711
20.02.2024
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
ILPO
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Natural Person
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| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2255 | |
| EPO | Filing, Examination, Granting | 10492 | |
| Japan | Filing, Examination, Granting | 2315 | |
| South Korea | Filing, Examination, Granting | 2449 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
22,251
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Abstract[English]
There is provided a quantum processor comprising a plurality of qubits, wherein the qubits are arranged such that direct interactions between any two qubits are suppressed, a harmonic oscillator mode coupled transversally to the plurality of qubits, a plurality of adiabatic driving lines associated with said plurality of qubits, wherein each adiabatic driving line is configured for driving a respective qubit with an adiabatic driving signal and a control module configured to drive concurrently at least a first qubit and a second qubit by their respective adiabatic driving lines with a first and second adiabatic driving signals and adjust a first waveform of the first adiabatic driving signal and a second waveform of the second adiabatic driving signal to establish a ZZ gate between the at least first and second qubits.[French]
L'invention concerne un processeur quantique comprenant une pluralité de bits quantiques, les bits quantiques étant agencés de sorte que des interactions directes entre deux bits quantiques quelconques sont supprimées, un mode d'oscillateur harmonique couplé de manière transversale à la pluralité de bits quantiques, une pluralité de lignes de commande adiabatiques associées à ladite pluralité de bits quantiques. Chaque ligne de commande adiabatique est conçue pour commander un bit quantique respectif avec un signal de commande adiabatique et un module de commande conçu pour commander simultanément au moins un premier bit quantique et un second bit quantique par leurs lignes de commande adiabatiques respectives avec des premier et second signaux de commande adiabatiques, et pour ajuster une première forme d'onde du premier signal de commande adiabatique et une seconde forme d'onde du second signal de commande adiabatique pour établir une grille ZZ entre lesdits au moins un premier et un second bits quantiques.