WO2025133793 - METALLIC SOURCE/DRAIN WITH STRESS FOR ADVANCED LOGIC TRANSISTORS
National phase entry is expected:
Publication Number
WO/2025/133793
Publication Date
26.06.2025
International Application No.
PCT/IB2024/062224
International Filing Date
04.12.2024
Title **
[English]
METALLIC SOURCE/DRAIN WITH STRESS FOR ADVANCED LOGIC TRANSISTORS
[French]
SOURCE/DRAIN MÉTALLIQUE À CONTRAINTE POUR TRANSISTORS LOGIQUES AVANCÉS
Applicants **
APPLIED MATERIALS, INC.
Inventors
BREIL, Nicolas
COLOMBEAU, Benjamin
PRANATHARTHIHARAN, Balasubramanian
VYAS, Pratik
PAL, Ashish
BAZIZI, El Mehdi
Priority Data
18/391,056
20.12.2023
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
| * | |
International Searching Authority |
ILPO
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1983 | |
| EPO | Filing, Examination, Granting | 11565 | |
| Japan | Filing, Examination, Granting | 2047 | |
| South Korea | Filing, Examination, Granting | 1848 | |
| USA | Filing, Examination, Granting | 7140 |
Total:
24,583
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Abstract[English]
A system and method for fabricating a gate all-around (GAA) field effect transistor (FET) is disclosed. The method includes: forming a plurality of epitaxy layers on a substrate, wherein a formed epitaxy layer includes a plurality of doped channels, a plurality of metal channels, and a dummy gate; depositing a spacer in a source/drain cavity, wherein at least a portion of the spacer is deposited on the dummy gate of the formed epitaxy layer; partially etching the plurality of metal channels to create a plurality of voids; depositing an inner spacer in each void of the plurality of voids; and depositing a stressed metal filler in the source/drain cavity.[French]
L'invention concerne un système et un procédé de fabrication d'un transistor à effet de champ (FET) à grille enveloppante (GAA). Le procédé consiste à : former une pluralité de couches épitaxiées sur un substrat, une couche épitaxiée formée comprenant une pluralité de canaux dopés, une pluralité de canaux métalliques et une grille factice ; déposer un espaceur dans une cavité de source/drain, au moins une portion de l'espaceur étant déposée sur la grille factice de la couche épitaxiée formée ; graver partiellement la pluralité de canaux métalliques pour créer une pluralité de vides ; déposer un espaceur interne dans chaque vide de la pluralité de vides ; et déposer une charge métallique à contrainte dans la cavité de source/drain.