WO2025017481 - INTEGRATED RANDOM ACCESS MEMORY USING INVERTER LOOPS
National phase entry:
Publication Number
WO/2025/017481
Publication Date
23.01.2025
International Application No.
PCT/IB2024/056900
International Filing Date
16.07.2024
Title **
[English]
INTEGRATED RANDOM ACCESS MEMORY USING INVERTER LOOPS
[French]
MÉMOIRE VIVE INTÉGRÉE UTILISANT DES BOUCLES D'ONDULEUR
Applicants **
TAALAS INC.
Inventors
BAJIC, Ljubisa
Priority Data
63/527,825
20.07.2023
US
63/546,920
01.11.2023
US
18/769,849
11.07.2024
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CIPO
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2530 | |
| EPO | Filing, Examination, Granting | 14931 | |
| Japan | Filing, Examination, Granting | 2328 | |
| South Korea | Filing, Examination, Granting | 2490 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
27,019
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
Methods and systems which involve computer memories are disclosed herein. The methods and systems involve integrated Random Access Memory (RAM) using loops of inverters. A disclosed RAM comprises a set of loops of inverters. The loops of inverters in the set of loops of inverters are addressable using a set of corresponding addresses. The RAM further comprises a write circuit configured to write a value to a first loop of inverters when provided with a corresponding address for the first loop of inverters. The first loop of inverters is in the set of loops of inverters and the corresponding address is in the set of corresponding addresses. The RAM further comprises a read circuit configured to read the value from the first loop of inverters when provided with the corresponding address.[French]
Sont divulgués dans la présente invention des procédés et des systèmes qui impliquent des mémoires d'ordinateur. Les procédés et les systèmes impliquent une mémoire vive intégrée (RAM) utilisant des boucles d'onduleurs. Une RAM divulguée comprend un ensemble de boucles d'onduleurs. Les boucles d'onduleurs de l'ensemble de boucles d'onduleurs sont adressables au moyen d'un ensemble d'adresses correspondantes. La RAM comprend en outre un circuit d'écriture configuré pour écrire une valeur dans une première boucle d'onduleurs lorsqu'une adresse correspondante pour la première boucle d'onduleurs est fournie. La première boucle d'onduleurs se trouve dans l'ensemble de boucles d'onduleurs et l'adresse correspondante se trouve dans l'ensemble d'adresses correspondantes. La RAM comprend en outre un circuit de lecture configuré pour lire la valeur dans la première boucle d'onduleurs lorsque l'adresse correspondante est fournie.