WO2024246877 - PARALLELIZED BOOT SEQUENCE
National phase entry is expected:
Publication Number
WO/2024/246877
Publication Date
05.12.2024
International Application No.
PCT/IB2024/055915
International Filing Date
18.06.2024
Title **
[English]
PARALLELIZED BOOT SEQUENCE
[French]
SÉQUENCE D'AMORÇAGE PARALLÉLISÉE
Applicants **
ADVANCED MICRO DEVICES, INC.
Inventors
SAMBAMURTHY, Sriram
PAUL, Indrani
BRANDL, Kevin M.
MAGRO, James R.
YU, Zhao Hui
HOUSTY, Oswin E.
Priority Data
63/505,125
31.05.2023
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| Number of Office Actions | * |
| * | |
International Searching Authority |
MOIP
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
|
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2271 | |
| EPO | Filing, Examination, Granting | 13495 | |
| Japan | Filing, Examination, Granting | 2386 | |
| South Korea | Filing, Examination, Granting | 1957 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
24,849
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
The disclosed device includes multiple special purpose processors that are configured to perform, in parallel, a power on transition sequence for the device, which can involve restoring a data state of components of the device using data stored in local storages of the special purpose processors. Various other methods, systems, and computer-readable media are also disclosed.[French]
Le dispositif divulgué comprend de multiples processeurs à usage spécial qui sont conçus pour mettre en oeuvre, en parallèle, une séquence de transition de puissance pour le dispositif, qui peut consister à restaurer un état de données de composants du dispositif à l'aide de données stockées dans des mémoires locales des processeurs à usage spécial. Divers autres procédés, systèmes et supports lisibles par ordinateur sont également divulgués.