WO2025040958 - COMPUTER-IMPLEMENTED METHOD AND SYSTEM FOR DETECTION OF AN EMULATOR
National phase entry is expected:
Publication Number
WO/2025/040958
Publication Date
27.02.2025
International Application No.
PCT/IB2024/053884
International Filing Date
22.04.2024
Title **
[English]
COMPUTER-IMPLEMENTED METHOD AND SYSTEM FOR DETECTION OF AN EMULATOR
[French]
PROCÉDÉ ET SYSTÈME MIS EN ŒUVRE PAR ORDINATEUR POUR LA DÉTECTION D'UN ÉMULATEUR
Applicants **
MAYHEM STUDIOS PRIVATE LIMITED
Inventors
SINGH, Shashank Kumar
Priority Data
202311056795
24.08.2023
IN
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
MOIP
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2247 | |
| EPO | Filing, Examination, Granting | 14140 | |
| Japan | Filing, Examination, Granting | 2315 | |
| South Korea | Filing, Examination, Granting | 1871 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
25,313
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
The present invention provides a computer-implemented method (100) for a detection of an emulator in an operating device (50) The method includes generating an instruction set comprising an emulator detection code capable to be run on the processors (52) of the operating device (50). The method further includes mapping the instruction set, with a plurality of flags to allocate a memory page. Further, the instruction set is stored as instruction cache. Thereafter, the mapped instruction set is executed, by the processors (52), for the detection of the emulator. The instruction set is being generated in such a way that the processors (52) operate only after executing the said mapped instruction set. The execution of the said mapped instruction includes running the emulator detection code in a predetermined manner, thereby confirming the detection of the emulator in the operating device (50).[French]
La présente invention concerne un procédé mis en œuvre par ordinateur (100) pour la détection d'un émulateur dans un dispositif d'exploitation (50), ledit procédé consistant à générer un ensemble d'instructions comprenant un code de détection d'émulateur pouvant être exécuté sur les processeurs (52) du dispositif d'exploitation (50). Le procédé consiste également à mapper l'ensemble d'instructions avec une pluralité de drapeaux pour attribuer une page de mémoire. De plus, l'ensemble d'instructions est stocké sous la forme d'une mémoire cache d'instructions. Ensuite, l'ensemble d'instructions mappé est exécuté par les processeurs (52) pour la détection de l'émulateur. L'ensemble d'instructions est généré de sorte que les processeurs (52) fonctionnent uniquement après l'exécution dudit ensemble d'instructions mappé. L'exécution de ladite instruction mappée consiste à exécuter le code de détection d'émulateur d'une manière prédéterminée, ce qui permet de confirmer la détection de l'émulateur dans le dispositif d'exploitation (50).