WO2025177017 - A TRANSISTOR STRESS STATE MODEL AND ITS APPLICATIONS
National phase entry is expected:
Publication Number
WO/2025/177017
Publication Date
28.08.2025
International Application No.
PCT/IB2024/051605
International Filing Date
20.02.2024
Title **
[English]
A TRANSISTOR STRESS STATE MODEL AND ITS APPLICATIONS
[French]
MODÈLE D'ÉTAT DE CONTRAINTE DE TRANSISTOR ET SES APPLICATIONS
Applicants **
SIEMENS INDUSTRY SOFTWARE INC.
Inventors
EGGERSGLUESS, Stephan
GLOWATZ, Andreas
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
EPO
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2383 | |
| EPO | Filing, Examination, Granting | 14207 | |
| Japan | Filing, Examination, Granting | 2511 | |
| South Korea | Filing, Examination, Granting | 2637 | |
| USA | Filing, Examination, Granting | 6540 |
Total:
28,278
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Abstract[English]
A, preferably computer-implemented, method comprising the step of determining one or more latent defects in an integrated circuit based on a stress target, the integrated circuit comprising at least one instance of a library cell, preferably from a plurality of library cells, wherein the library cell comprises or is associated with the stress target, wherein the stress target of the library cell is indicative of one or more stress states of at least one transistor of the library cell.[French]
Est divulgué un procédé, de préférence mis en œuvre par ordinateur, comprenant l'étape consistant à déterminer au moins un défaut latent dans un circuit intégré en fonction d'une cible de contrainte, le circuit intégré comprenant au moins une instance d'une cellule de bibliothèque, de préférence parmi une pluralité de cellules de bibliothèque, la cellule de bibliothèque comprenant la cible de contrainte ou étant associée à celle-ci, la cible de contrainte de la cellule de bibliothèque indiquant au moins un état de contrainte d'au moins un transistor de la cellule de bibliothèque.