WO2025093927 - SYSTEMS, METHODS, AND APPARATUS FOR ACCESSING MEMORY WITH DIE-TO-DIE INTERFACES
National phase entry is expected:
Publication Number
WO/2025/093927
Publication Date
08.05.2025
International Application No.
PCT/IB2024/000621
International Filing Date
01.11.2024
Title **
[English]
SYSTEMS, METHODS, AND APPARATUS FOR ACCESSING MEMORY WITH DIE-TO-DIE INTERFACES
[French]
SYSTÈMES, PROCÉDÉS ET APPAREIL POUR ACCÉDER À UNE MÉMOIRE AVEC DES INTERFACES PUCE À PUCE
Applicants **
SAMSUNG ELECTRONICS CO., LTD.
Inventors
KIM, Soon Ju
JEONG, Hyoun Kwon
JEONG, Soogil
Priority Data
63/547,142
02.11.2023
US
63/568,408
21.03.2024
US
18/935,341
01.11.2024
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| Number of Office Actions | * |
| * | |
International Searching Authority |
MOIP
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
|
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2715 | |
| EPO | Filing, Examination, Granting | 15612 | |
| Japan | Filing, Examination, Granting | 2331 | |
| South Korea | Filing, Examination, Granting | 1932 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
27,330
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
An apparatus may include a die including a memory interface, a die-to-die (D2D) circuit comprising a D2D interface, and an intermediate section connected between the memory interface and the D2D interface, wherein the intermediate section comprises a transaction converter. The intermediate section may be configured to transfer data through the D2D interface using a protocol. The D2D interface may be configured to transfer data using flow control. The D2D interface may be configured to transfer data using a raw format.[French]
Un appareil peut comprendre une puce comprenant une interface de mémoire, un circuit de puce à puce (D2D) comprenant une interface D2D, et une section intermédiaire connectée entre l'interface de mémoire et l'interface D2D, la section intermédiaire comprenant un convertisseur de transaction. La section intermédiaire peut être conçue pour transférer des données par l'intermédiaire de l'interface D2D à l'aide d'un protocole. L'interface D2D peut être conçue pour transférer des données à l'aide d'une commande de flux. L'interface D2D peut être conçue pour transférer des données à l'aide d'un format brut.