WO2024121619 - PCB DESIGN TO IMPROVE HFM CONNECTOR PERFORMANCE
National phase entry:
Publication Number
WO/2024/121619
Publication Date
13.06.2024
International Application No.
PCT/IB2023/000735
International Filing Date
05.12.2023
Title **
[English]
PCB DESIGN TO IMPROVE HFM CONNECTOR PERFORMANCE
[French]
CONCEPTION DE CARTE DE CIRCUIT IMPRIMÉ POUR AMÉLIORER LES PERFORMANCES D'UN CONNECTEUR HFM
Applicants **
NIO TECHNOLOGY (ANHUI) CO., LTD.
Inventors
LI, Tiejun
XU, Jianfeng
LIN, Futing
Priority Data
63/430,508
06.12.2022
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| Number of Office Actions | * |
| * | |
International Searching Authority |
EPO
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
|
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2185 | |
| EPO | Filing, Examination, Granting | 10369 | |
| Japan | Filing, Examination, Granting | 2294 | |
| South Korea | Filing, Examination, Granting | 2309 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
21,897
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Contact Us
Abstract[English]
A printed circuit board and an apparatus including the printed circuit board are described. The printed circuit board includes a plurality of layers; a footprint fabricated on an outer layer of the plurality of layers; a plurality of holes 215 corresponding to signal pins 111 and a ground pin 112, wherein the plurality of holes are included in the footprint. The printed circuit board includes a ground guard including: ground pads, ground layers, and a set of vias 230. The vias 230 are located on the ground pads and connect the ground layers. The vias 230 are located between a hole 205-e corresponding to the ground pin and at least one hole 205-a corresponding to one signal pin of the plurality of signal pins in a direction parallel to a plane of the plurality of layers. A quantity of the vias is based on satisfying a signal integrity threshold associated with the at least one signal pin of the plurality of signal pins.[French]
Une carte de circuit imprimé et un appareil comprenant la carte de circuit imprimé sont décrits. La carte de circuit imprimé comprend une pluralité de couches; une empreinte fabriquée sur une couche externe de la pluralité de couches; une pluralité de trous correspondant aux broches de signaux (111) et une broche de masse (112), la pluralité de trous étant incluse dans l'empreinte. La carte de circuit imprimé comprend une garde de masse comprenant : des plots de masse, des couches de masse et un ensemble de trous d'interconnexion (230). Les trous d'interconnexion (230) sont situés sur les plots de masse et connectent les couches de masse. Les trous d'interconnexion (230) sont situés entre un trou (205-e) correspondant à la broche de masse et au moins un trou (205-a) correspondant une broche de signaux de la pluralité de broches de signaux dans une direction parallèle à un plan de la pluralité de couches. Une quantité des trous d'interconnexion est basée sur la satisfaction d'un seuil d'intégrité de signal associé à la ou aux broches de signaux de la pluralité de broches de signaux.