WO2023170476 - METHOD AND APPARATUS FOR AVOIDING PACKET MIS-ORDERING WHEN USING VIRTUAL CHANNEL FIFOS IN A DIRECT INTERCONNECT COMPUTER NETWORK
National phase entry is expected:
Publication Number
WO/2023/170476
Publication Date
14.09.2023
International Application No.
PCT/IB2023/000149
International Filing Date
03.03.2023
Title **
[English]
METHOD AND APPARATUS FOR AVOIDING PACKET MIS-ORDERING WHEN USING VIRTUAL CHANNEL FIFOS IN A DIRECT INTERCONNECT COMPUTER NETWORK
[French]
PROCÉDÉ ET APPAREIL POUR ÉVITER UN MAUVAIS ORDONNANCEMENT DE PAQUETS LORS DE L'UTILISATION DE DIFO DE VOIES VIRTUELLES DANS UN RÉSEAU INFORMATIQUE À INTERCONNEXION DIRECTE
Applicants **
ROCKPORT NETWORKS INC.
Inventors
JENNINGS, Alan, James
MES, Ian, Antoine
Priority Data
63/318,991
11.03.2022
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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| Number of Office Actions | * |
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International Searching Authority |
CIPO
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1954 | |
| EPO | Filing, Examination, Granting | 11600 | |
| Japan | Filing, Examination, Granting | 1868 | |
| South Korea | Filing, Examination, Granting | 1460 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
21,622
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
A method for avoiding packet mis-ordering when routing a flow of packets in a direct interconnect network along a path from a source node to a destination node using virtual channel FIFOs. The method involves assigning a VC FIFO buffer for an input port in the next node along the path from the source node to the destination node via a next-hop VC allocation table (NVT), which encodes VC FIFO buffer availability for all packets identified as part of the flow of packets.[French]
L'invention concerne un procédé permettant d'éviter un mauvais ordonnancement de paquets lors du routage d'un flux de paquets dans un réseau à interconnexion directe dans la longueur d'un trajet allant d'un nœud source à un nœud de destination à l'aide de FIFO de voie virtuelle. Le procédé consiste à attribuer un tampon FIFO VC pour un port d'entrée dans le nœud suivant, dans la longueur du trajet allant du nœud source au nœud de destination, par l'intermédiaire d'une table d'attribution VC de saut suivant (NVT), qui code la disponibilité de tampon FIFO VC pour tous les paquets identifiés en tant qu'éléments du flux de paquets.