WO2023067386 - MANUFACTURING AND REUSE OF SEMICONDUCTOR SUBSTRATES
National phase entry:
Publication Number
WO/2023/067386
Publication Date
27.04.2023
International Application No.
PCT/IB2022/000607
International Filing Date
21.10.2022
Title **
[English]
MANUFACTURING AND REUSE OF SEMICONDUCTOR SUBSTRATES
[French]
FABRICATION ET RÉUTILISATION DE SUBSTRATS À SEMI-CONDUCTEURS
Applicants **
INFINEON TECHNOLOGIES AG
Inventors
GOLLER, Bernhard
BINTER, Alexander Christian
HOECHBAUER, Tobias, Franz Wolfgang
HUBER, Martin
MODER, Iris
PICCIN, Matteo
SANTOS RODRIGUEZ, Francisco, Javier
SCHULZE, Hans-Joachim
Priority Data
63/270,599
22.10.2021
US
17/743,006
12.05.2022
US
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
EPO
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2679 | |
| EPO | Filing, Examination, Granting | 16494 | |
| Japan | Filing, Examination, Granting | 2638 | |
| South Korea | Filing, Examination, Granting | 3020 | |
| USA | Filing, Examination, Granting | 6740 |
Total:
31,571
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
A method of processing a semiconductor wafer includes: forming one or more epitaxial layers over a first main surface of the semiconductor wafer; forming one or more porous layers in the semiconductor wafer or in the one or more epitaxial layers, wherein the semiconductor wafer, the one or more epitaxial layers and the one or more porous layers collectively form a substrate; forming doped regions of a semiconductor device in the one or more epitaxial layers; and after forming the doped regions of the semiconductor device, separating a non- porous part of the semiconductor wafer from a remainder of the substrate along the one or more porous layers.[French]
Un procédé de traitement d'une tranche de semi-conducteur consiste à : former une ou plusieurs couches épitaxiales sur une première surface principale de la tranche de semi-conducteur ; former une ou plusieurs couches poreuses dans la tranche de semi-conducteur ou dans la couche ou les couches épitaxiales, la tranche de semi-conducteur, la ou les couches épitaxiales et la ou les couches poreuses formant collectivement un substrat ; former des régions dopées d'un dispositif à semi-conducteur dans la couche ou les couches épitaxiales ; et après avoir formé les régions dopées du dispositif à semi-conducteur, séparer une partie non poreuse de la tranche de semi-conducteur d'un reste du substrat le long de la couche ou des couches poreuses.