WO2026099105 - VERFAHREN ZUM SYNCHRONISIEREN EINES EINSCHALTVORGANGS VON PARALLELGESCHALTETEN TRANSISTOREN
National phase entry is expected:
Publication Number
WO/2026/099105
Publication Date
15.05.2026
International Application No.
PCT/EP2025/081647
International Filing Date
03.11.2025
Title **
[German]
VERFAHREN ZUM SYNCHRONISIEREN EINES EINSCHALTVORGANGS VON PARALLELGESCHALTETEN TRANSISTOREN
[English]
METHOD FOR SYNCHRONISING A SWITCH-ON OPERATION OF PARALLEL-CONNECTED TRANSISTORS
[French]
PROCÉDÉ DE SYNCHRONISATION D'UNE OPÉRATION DE MISE EN CIRCUIT DE TRANSISTORS MONTÉS EN PARALLÈLE
Applicants **
ROBERT BOSCH GMBH
Inventors
SYED, Hadiuzzaman
ALAM, Muhammad Muneeb
STREIT, Jochen
RUOFF, Dominik Alexander
Priority Data
102024210760.3
08.11.2024
DE
Application details
| Total Number of Claims/PCT | * |
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| Number of Multi-Dependent Claims | * |
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International Searching Authority |
EPO
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1907 | |
| EPO | Filing, Examination, Granting | 8118 | |
| Japan | Filing, Examination, Granting | 2047 | |
| South Korea | Filing, Examination, Granting | 1798 | |
| USA | Filing, Examination, Granting | 5940 |
Total:
19,810
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Abstract[German]
) während des Einschaltvorgangs der Transistoren (2), - Bestimmen (102) individueller Verzögerungen (∆td1, ∆td2) von Schalttransienten im Rahmen des Einschaltvorgangs für jeden Transistor (2) auf Basis von Steigungsänderungen in dem jeweiligen Verlauf der Gate-Source-Spannung, - Initiieren (103) einer Konfiguration wenigstens eines Gate-Treibers (3) auf Basis der bestimmten individuellen Verzögerungen, um den Einschaltvorgang der parallelgeschalteten Transistoren (2) zu synchronisieren, wobei der wenigstens eine Gate-Treiber (3) zum Ansteuern der Transistoren (2) verwendet wird. Ferner betrifft die Erfindung ein Leistungsmodul, ein Computerprogramm, eine Vorrichtung sowie ein Speichermedium zu diesem Zweck.[English]
) during the switch-on operation of the transistors (2); - determining (102) individual delays (∆td1, ∆td2) of switching transients within the switch-on operation for each transistor (2) on the basis of slope changes in the respective curve of the gate-source voltage; - initiating (103) configuration of at least one gate driver (3) on the basis of the determined individual delays in order to synchronise the switch-on operation of the parallel-connected transistors (2), wherein the at least one gate driver (3) is used to control the transistors (2). The invention also relates to a power module, a computer program, a device, and a storage medium for this purpose.[French]
) pendant l'opération de mise en circuit des transistors (2); déterminer (102) des retards (∆td1, ∆td2) individuels de transitoires de commutation dans le cadre de l'opération de mise en circuit pour chaque transistor (2) sur la base de variations de pente dans la courbe respective de la tension grille-source, initier (103) une configuration d'au moins un pilote de grille (3) sur la base des retards individuels déterminés pour synchroniser l'opération de mise en circuit des transistors (2) montés en parallèle, le ou les pilotes de grille (3) étant utilisés pour commander les transistors (2). Cette invention concerne en outre un module de puissance, un programme informatique, un dispositif ainsi qu'un support de stockage à cet effet.