WO2026068749 - CHIPLET ASSEMBLY AND A METHOD FOR TRANSLATING MEMORY ACCESS COMMANDS IN THE CHIPLET ASSEMBLY
National phase entry is expected:
Publication Number
WO/2026/068749
Publication Date
02.04.2026
International Application No.
PCT/EP2025/077692
International Filing Date
26.09.2025
Title **
[English]
CHIPLET ASSEMBLY AND A METHOD FOR TRANSLATING MEMORY ACCESS COMMANDS IN THE CHIPLET ASSEMBLY
[French]
ENSEMBLE MICROPUCE ET PROCÉDÉ DE TRADUCTION DE COMMANDES D'ACCÈS À LA MÉMOIRE DANS L'ENSEMBLE MICROPUCE
Applicants **
ROBERT BOSCH GMBH
Inventors
COUPE, David
Priority Data
102024209306.8
26.09.2024
DE
Application details
| Total Number of Claims/PCT | * |
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| Number of Multi-Dependent Claims | * |
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International Searching Authority |
EPO
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1880 | |
| EPO | Filing, Examination, Granting | 8180 | |
| Japan | Filing, Examination, Granting | 2020 | |
| South Korea | Filing, Examination, Granting | 1743 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
18,563
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Abstract[English]
The invention relates to a chiplet assembly (1) comprising: - A shared electronic memory (2), - A system management controller (3), the system management controller (3) comprising a memory interface (4) for accessing the shared electronic memory (2), - A System-on-Chip (5), the System-on-Chip (5) being connected to the system management controller (3) via a physical interface (6), the physical interface (6) being designed to enable an access of the System-on-Chip (5) to electronic memories, - A substrate (7) for accommodating the system management controller (3) and the System-on-Chip (5). The invention further relates to a method for translating memory access commands in the chiplet assembly.[French]
L'invention concerne un ensemble de micropuces (1) comprenant : une mémoire électronique partagée (2) ; un dispositif de commande de gestion de système (3), le contrôleur de gestion de système (3) comprenant une interface mémoire (4) pour accéder à la mémoire électronique partagée (2) ; un système sur puce (5), le système sur puce (5) étant connecté au dispositif de commande de gestion de système (3) par l'intermédiaire d'une interface physique (6), l'interface physique (6) étant conçue pour permettre un accès du système sur puce (5) à des mémoires électroniques ; un substrat (7) pour recevoir le dispositif de commande de gestion de système (3) et le système sur puce (5). L'invention concerne en outre un procédé de traduction de commandes d'accès à la mémoire dans l'ensemble micropuce.