WO2026118778 - MEMORY
National phase entry is expected:
Publication Number
WO/2026/118778
Publication Date
11.06.2026
International Application No.
PCT/CN2025/132848
International Filing Date
05.11.2025
Title **
[English]
MEMORY
[French]
MÉMOIRE
[Chinese]
存储器
Applicants **
CXMT CORPORATION
Inventors
LIANG, Binxi
ZHANG, Zufa
Priority Data
202411784548.X
02.12.2024
CN
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1575 | |
| EPO | Filing, Examination, Granting | 11629 | |
| Japan | Filing, Examination, Granting | 2016 | |
| South Korea | Filing, Examination, Granting | 1794 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
21,754
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Abstract[English]
The embodiments of the present application relate to the field of memories. Provided is a memory, the memory comprising a first chip, a second chip, a third chip and a fourth chip which are sequentially stacked in a first direction, wherein a logic circuit is formed on the first chip, a first memory array is formed on the second chip, a core area circuit is formed on the third chip, and a second memory array is formed on the fourth chip.[French]
Les modes de réalisation de la présente demande se rapportent au domaine des mémoires. La présente demande concerne une mémoire, la mémoire comprenant une première puce, une seconde puce, une troisième puce et une quatrième puce qui sont empilées séquentiellement dans une première direction, un circuit logique étant formé sur la première puce, une première matrice de mémoire étant formée sur la seconde puce, un circuit de zone centrale étant formé sur la troisième puce, et un seconde matrice de mémoire étant formée sur la quatrième puce.[Chinese]
本申请实施例涉及存储器领域，提供一种存储器，包括沿第一方向依次层叠的第一芯片、第二芯片、第三芯片和第四芯片，其中，所述第一芯片上形成有逻辑电路，所述第二芯片上形成有第一存储阵列，所述第三芯片上形成有核心区电路，所述第四芯片上形成有第二存储阵列。