WO2026118617 - INTEGRATED CIRCUIT PACKAGE
National phase entry is expected:
Publication Number
WO/2026/118617
Publication Date
11.06.2026
International Application No.
PCT/CN2025/121465
International Filing Date
16.09.2025
Title **
[English]
INTEGRATED CIRCUIT PACKAGE
[French]
BOÎTIER DE CIRCUIT INTÉGRÉ
[Chinese]
集成电路封装
Applicants **
CXMT CORPORATION
Inventors
LEE, Tzung-han
LIU, Xiaoping
LIU, Chih-cheng
Priority Data
202411798666.6
06.12.2024
CN
Application details
| Total Number of Claims/PCT | * |
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International Searching Authority |
CNIPA
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1570 | |
| EPO | Filing, Examination, Granting | 11616 | |
| Japan | Filing, Examination, Granting | 2017 | |
| South Korea | Filing, Examination, Granting | 1780 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
21,723
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Abstract[English]
Embodiments of the present disclosure relate to the field of semiconductors, and provide an integrated circuit package, comprising: a memory chip and a logic chip; an interface connection structure, comprising a physical layer and an electrically conductive post connected to the physical layer, the physical layer comprising a first physical layer, a second physical layer, and a logic connection layer, the first physical layer being a physical layer of the memory chip, the second physical layer being a physical layer of the logic chip, and both the first physical layer and the second physical layer being connected to the logic connection layer.[French]
Des modes de réalisation de la présente divulgation se rapportent au domaine des semi-conducteurs et concernent un boîtier de circuit intégré, comprenant : une puce mémoire et une puce logique ; une structure de connexion d'interface, comprenant une couche physique et un montant électriquement conducteur connecté à la couche physique, la couche physique comprenant une première couche physique, une seconde couche physique et une couche de connexion logique, la première couche physique étant une couche physique de la puce mémoire, la seconde couche physique étant une couche physique de la puce logique, et la première couche physique et la seconde couche physique étant toutes deux connectées à la couche de connexion logique.[Chinese]
本公开实施例涉及半导体领域，提供一种集成电路封装，包括：存储芯片和逻辑芯片；接口连接结构，接口连接结构包括物理层和与物理层连接的导电柱，物理层包括第一物理层、第二物理层和逻辑连接层，第一物理层为存储芯片的物理层，第二物理层为逻辑芯片的物理层，第一物理层和第二物理层均与逻辑连接层连接。