WO2026108029 - METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTURE PREPARED THEREBY
National phase entry is expected:
Publication Number
WO/2026/108029
Publication Date
28.05.2026
International Application No.
PCT/CN2025/082239
International Filing Date
13.03.2025
Title **
[English]
METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTURE PREPARED THEREBY
[French]
PROCÉDÉ DE PRÉPARATION D'UNE STRUCTURE SEMI-CONDUCTRICE ET STRUCTURE SEMI-CONDUCTRICE AINSI PRÉPARÉE
[Chinese]
一种半导体结构的制备方法及其半导体结构
Applicants **
CXMT CORPORATION
Inventors
REN, Peng
Priority Data
202411679081.2
21.11.2024
CN
Application details
| Total Number of Claims/PCT | * |
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International Searching Authority |
CNIPA
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1864 | |
| EPO | Filing, Examination, Granting | 14189 | |
| Japan | Filing, Examination, Granting | 2326 | |
| South Korea | Filing, Examination, Granting | 2442 | |
| USA | Filing, Examination, Granting | 4740 |

Total:
25,561
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Abstract[English]
A method for preparing a semiconductor structure, and a semiconductor structure. The preparation method comprises: providing a substrate, and forming a first trench on the substrate; filling the first trench with a first initial electrically conductive structure and covering the surface of the substrate; using a first polishing process to remove a portion of the first initial electrically conductive structure, so as to form a first electrically conductive structure, wherein the first electrically conductive structure is located in the first trench, and the surface of the first electrically conductive structure has a first recess; forming a barrier layer, which at least covers the first recess; and forming a second electrically conductive structure on the barrier layer, wherein the second electrically conductive structure is electrically connected to the barrier layer.[French]
Procédé de préparation d'une structure semi-conductrice et structure semi-conductrice. Le procédé de préparation comprend : la fourniture d'un substrat et la formation d'une première tranchée sur le substrat ; le remplissage de la première tranchée avec une première structure électriquement conductrice initiale et le recouvrement de la surface du substrat ; l'utilisation d'un premier procédé de polissage pour retirer une partie de la première structure électriquement conductrice initiale, de façon à former une première structure électriquement conductrice, la première structure électriquement conductrice étant située dans la première tranchée et la surface de la première structure électriquement conductrice présentant un premier évidement ; la formation d'une couche barrière recouvrant au moins le premier évidement ; et la formation d'une seconde structure électriquement conductrice sur la couche barrière, la seconde structure électriquement conductrice étant connectée électriquement à la couche barrière.[Chinese]
一种半导体结构的制备方法和半导体结构,制备方法包括:提供基底,在基底上形成第一沟槽;第一初始导电结构填满第一沟槽且覆盖基底表面;采用第一研磨工艺去除部分第一初始导电结构以形成第一导电结构,第一导电结构位于第一沟槽内且第一导电结构表面具有第一凹陷;形成阻挡层,阻挡层至少覆盖第一凹陷;在阻挡层上形成第二导电结构,第二导电结构与阻挡层电连接。