WO2025209054 - STORAGE DEVICE, AND SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
National phase entry is expected:
Publication Number
WO/2025/209054
Publication Date
09.10.2025
International Application No.
PCT/CN2025/078471
International Filing Date
21.02.2025
Title **
[English]
STORAGE DEVICE, AND SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
[French]
DISPOSITIF DE STOCKAGE, ET STRUCTURE SEMI-CONDUCTRICE ET SON PROCÉDÉ DE FABRICATION
[Chinese]
存储器件、半导体结构及其制作方法
Applicants **
CXMT CORPORATION
Inventors
YU, Yexiao
ZHANG, Yang
LIU, Zhongming
TANG, Wenshuai
WANG, Feng
Priority Data
202410398933.4
03.04.2024
CN
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1719 | |
| EPO | Filing, Examination, Granting | 11600 | |
| Japan | Filing, Examination, Granting | 2181 | |
| South Korea | Filing, Examination, Granting | 2107 | |
| USA | Filing, Examination, Granting | 4740 |

Total:
22,347
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Abstract[English]
Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate, wherein the substrate comprises a plurality of active structures arranged at intervals in a first direction and a second direction, each active structure comprises a first active portion and a second active portion, the substrate has a first surface, and the second active portion extends towards the first surface along the first active portion, and has a first end surface in the direction facing the first surface; contact structures, wherein the contact structures are located on the first end surfaces of the second active portions; and a barrier layer, which is located on the first surface and covers parts of the side walls of the second active portions and parts of the side walls of the contact structures.[French]
Sont divulgués une structure semi-conductrice et son procédé de fabrication. La structure semi-conductrice comprend : un substrat, le substrat comprenant une pluralité de structures actives agencées à des intervalles dans une première direction et une seconde direction, chaque structure active comprenant une première partie active et une seconde partie active, le substrat comportant une première surface, et la seconde partie active s'étendant vers la première surface le long de la première partie active, et comportant une première surface d'extrémité dans la direction faisant face à la première surface ; des structures de contact, les structures de contact étant situées sur les premières surfaces d'extrémité des secondes parties actives ; et une couche barrière, qui est située sur la première surface et recouvre des parties des parois latérales des secondes parties actives et des parties des parois latérales des structures de contact.[Chinese]
公开了一种半导体结构及其制作方法,半导体结构包括:衬底,衬底包括多个沿第一方向以及第二方向间隔排布的有源结构,有源结构包括第一有源部和第二有源部;衬底包括第一表面,第二有源部沿第一有源部向第一表面延伸,并且在朝向第一表面的方向具有第一端面;接触结构,接触结构位于第二有源部的第一端面;阻挡层,位于第一表面上且覆盖部分第二有源部的侧壁和部分接触结构的侧壁。