WO2025218153 - ARRAY SUBSTRATE AND DISPLAY APPARATUS
National phase entry is expected:
Publication Number
WO/2025/218153
Publication Date
23.10.2025
International Application No.
PCT/CN2024/131206
International Filing Date
11.11.2024
Title **
[English]
ARRAY SUBSTRATE AND DISPLAY APPARATUS
[French]
SUBSTRAT DE RÉSEAU ET APPAREIL D'AFFICHAGE
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
Inventors
FANG, Zheng
YU, Lianfu
WU, Qian
DING, Yanping
LIANG, Pengxia
Priority Data
202410480562.4
19.04.2024
CN
202410501820.2
24.04.2024
CN
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2109 | |
| EPO | Filing, Examination, Granting | 14881 | |
| Japan | Filing, Examination, Granting | 2326 | |
| South Korea | Filing, Examination, Granting | 2475 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
26,531
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Abstract[English]
An array substrate includes a plurality of rows of subpixels; and a plurality of gate lines. At least four gate lines are configured to provide signals to one row of the a plurality of rows of subpixels. At least one gate line of the plurality of gate lines is between light emitting areas of the one row of subpixels and light emitting areas of a first adjacent row of subpixels. At least two gate lines of the plurality of gate lines are between the light emitting areas of the one row of subpixels and light emitting areas of a second adjacent row of subpixels. At least another one gate line of the plurality of gate lines crosses over the light emitting areas of the one row of subpixels. The first adjacent row of subpixels, the one row of subpixels, and the second adjacent row of subpixels are sequentially arranged.[French]
Est divulgué un substrat de réseau comprenant une pluralité de rangées de sous-pixels ; et une pluralité de lignes de grille. Au moins quatre lignes de grille sont configurées pour fournir des signaux à une rangée de la pluralité de rangées de sous-pixels. Au moins une ligne de grille de la pluralité de lignes de grille se trouve entre des zones électroluminescentes de ladite rangée de sous-pixels et des zones électroluminescentes d'une première rangée adjacente de sous-pixels. Au moins deux lignes de grille de la pluralité de lignes de grille se trouvent entre les zones électroluminescentes de ladite rangée de sous-pixels et des zones électroluminescentes d'une seconde rangée adjacente de sous-pixels. Au moins une autre ligne de grille de la pluralité de lignes de grille croise les zones électroluminescentes de ladite rangée de sous-pixels. La première rangée adjacente de sous-pixels, ladite rangée de sous-pixels et la seconde rangée adjacente de sous-pixels sont agencées de manière séquentielle.