WO2026020611 - SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND SEMICONDUCTOR DEVICE
National phase entry is expected:
Publication Number
WO/2026/020611
Publication Date
29.01.2026
International Application No.
PCT/CN2024/126304
International Filing Date
22.10.2024
Title **
[English]
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND SEMICONDUCTOR DEVICE
[French]
STRUCTURE SEMI-CONDUCTRICE ET SON PROCÉDÉ DE FABRICATION, ET DISPOSITIF À SEMICONDUCTEURS
[Chinese]
半导体结构及其制造方法、半导体器件
Applicants **
CXMT CORPORATION
Inventors
WANG, Yibo
Priority Data
202411022419.7
26.07.2024
CN
Application details
| Total Number of Claims/PCT | * |
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International Searching Authority |
CNIPA
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1858 | |
| EPO | Filing, Examination, Granting | 14180 | |
| Japan | Filing, Examination, Granting | 2328 | |
| South Korea | Filing, Examination, Granting | 2426 | |
| USA | Filing, Examination, Granting | 4740 |

Total:
25,532
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Abstract[English]
A semiconductor structure and a manufacturing method therefor, and a semiconductor device. The semiconductor structure comprises a substrate, wherein the substrate comprises a memory region, a peripheral region, and a transition region located between the memory region and the peripheral region, a first isolation structure being provided in the transition region; and a first trench, which is located in the isolation structure and extends in a first direction, wherein the depth of the first trench is less than the depth of the isolation structure. The semiconductor structure has a good performance.[French]
L'invention porte sur une structure semi-conductrice et son procédé de fabrication, ainsi qu'un dispositif à semi-conducteurs. La structure semi-conductrice comprend un substrat, le substrat comprenant une région de mémoire, une région périphérique et une région de transition située entre la région de mémoire et la région périphérique, une première structure d'isolation étant disposée dans la région de transition ; et une première tranchée, qui est située dans la structure d'isolation et s'étend dans une première direction, la profondeur de la première tranchée étant inférieure à la profondeur de la structure d'isolation. La structure semi-conductrice présente de bonnes performances.[Chinese]
一种半导体结构及其制造方法、半导体器件。该半导体结构包括衬底,衬底包括存储区、外围区以及位于存储区和外围区之间的过渡区,过渡区中有第一隔离结构。第一沟槽,位于隔离结构中,第一沟槽沿第一方向延伸;第一沟槽的深度小于隔离结构的深度。该半导体结构的性能良好。