WO2026020256 - ARRAY SUBSTRATE AND DISPLAY APPARATUS
National phase entry is expected:
Publication Number
WO/2026/020256
Publication Date
29.01.2026
International Application No.
PCT/CN2024/106639
International Filing Date
22.07.2024
Title **
[English]
ARRAY SUBSTRATE AND DISPLAY APPARATUS
[French]
SUBSTRAT DE RÉSEAU ET APPAREIL D'AFFICHAGE
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
Inventors
LI, Zhengkun
CHEN, Jiaxing
NIU, Zuoji
YANG, Zhongliu
AN, Yi
WANG, Yu
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2102 | |
| EPO | Filing, Examination, Granting | 15361 | |
| Japan | Filing, Examination, Granting | 2337 | |
| South Korea | Filing, Examination, Granting | 2340 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
26,880
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Abstract[English]
An array substrate including a plurality of pixel driving circuits is provided. A respective pixel driving circuit includes a driving transistor and a compensating transistor. An active layer of the compensating transistor includes a first portion and a second portion. The first portion and the second portion are spaced apart by an intermediate portion. An orthographic projection of the intermediate portion on a base substrate is non-overlapping with an orthographic projection of a gate electrode of the compensating transistor on the base substrate. The array substrate includes an interference prevention block. The interference prevention block is configured to be provided with a first voltage signal that is supplied to a cathode of a light emitting element in the array substrate. An orthographic projection of the interference prevent block on the base substrate at least partially overlaps with an orthographic projection of the intermediate portion on the base substrate.[French]
L'invention concerne un substrat de réseau comprenant une pluralité de circuits d'attaque de pixel. Un circuit d'attaque de pixel respectif comprend un transistor d'attaque et un transistor de compensation. Une couche active du transistor de compensation comprend une première partie et une seconde partie. La première partie et la seconde partie sont espacées par une partie intermédiaire. Une projection orthographique de la partie intermédiaire sur un substrat de base ne chevauche pas une projection orthographique d'une électrode de grille du transistor de compensation sur le substrat de base. Le substrat de réseau comprend un bloc de prévention d'interférence. Le bloc de prévention d'interférence est configuré pour recevoir un premier signal de tension qui est fourni à une cathode d'un élément électroluminescent dans le substrat de réseau. Une projection orthographique du bloc de prévention d'interférence sur le substrat de base chevauche au moins partiellement une projection orthographique de la partie intermédiaire sur le substrat de base.