WO2025025129 - ARRAY SUBSTRATE AND DISPLAY APPARATUS
National phase entry:
Publication Number
WO/2025/025129
Publication Date
06.02.2025
International Application No.
PCT/CN2023/110469
International Filing Date
01.08.2023
Title **
[English]
ARRAY SUBSTRATE AND DISPLAY APPARATUS
[French]
SUBSTRAT MATRICIEL ET APPAREIL D'AFFICHAGE
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
Inventors
DU, Mengmeng
HUANG, Yao
LIU, Tingliang
LIU, Lang
ZHANG, Yuxin
CAO, Xilei
FAN, Cong
XIANG, Zhiwei
DONG, Xiangdan
LI, Hanchao
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
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| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2209 | |
| EPO | Filing, Examination, Granting | 15749 | |
| Japan | Filing, Examination, Granting | 2325 | |
| South Korea | Filing, Examination, Granting | 2361 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
27,384
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
An array substrate is provided. The array substrate includes a first semiconductor material layer and a second semiconductor material layer on a side of the first semiconductor material layer away from a base substrate. The first semiconductor material layer includes at least active layers of the driving transistor and the data write transistor. The second semiconductor material layer includes at least an active layer of the compensating transistor. A first capacitance is at least partially formed between a gate connecting pad and at least one of the second semiconductor material layer or a first node connecting line. A second capacitance is formed between the first node connecting line and a respective second gate line. The first capacitance is greater than the second capacitance.[French]
L'invention propose un substrat matriciel. Le substrat matriciel comprend une première couche de matériau semi-conducteur et une seconde couche de matériau semi-conducteur sur un côté de la première couche de matériau semi-conducteur à l'opposé d'un substrat de base. La première couche de matériau semi-conducteur comprend au moins des couches actives du transistor d'attaque et du transistor d'écriture de données. La seconde couche de matériau semi-conducteur comprend au moins une couche active du transistor de compensation. Une première capacité est au moins partiellement formée entre un plot de connexion de grille et au moins l'une de la seconde couche de matériau semi-conducteur ou d'une première ligne de connexion de nœud. Une seconde capacité est formée entre la première ligne de connexion de nœud et une seconde ligne de grille respective. La première capacité est supérieure à la seconde capacité.