WO2023125334 - FIELD-PROGRAMMABLE GATE ARRAY (FPGA) CLUSTERS AND METHODS OF USING AN FPGA CLUSTER FOR HOMOMORPHIC ENCRYPTION ACCELERATION
National phase entry is expected:
Publication Number
WO/2023/125334
Publication Date
06.07.2023
International Application No.
PCT/CN2022/141698
International Filing Date
24.12.2022
Title **
[English]
FIELD-PROGRAMMABLE GATE ARRAY (FPGA) CLUSTERS AND METHODS OF USING AN FPGA CLUSTER FOR HOMOMORPHIC ENCRYPTION ACCELERATION
[French]
GRAPPES DE RÉSEAU PRÉDIFFUSÉ PROGRAMMABLE PAR L'UTILISATEUR (FPGA) ET PROCÉDÉS D'UTILISATION D'UNE GRAPPE DE FPGA POUR UNE ACCÉLÉRATION DE CRYPTAGE HOMOMORPHE
Applicants **
HUAWEI TECHNOLOGIES CO., LTD.
Inventors
LIAO, Haohao
SHANG, Zhiwei
TAN, Yin
Priority Data
17/566,337
30.12.2021
US
Application details
| Total Number of Claims/PCT | * |
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| Number of Drawings | * |
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International Searching Authority |
CNIPA
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1866 | |
| EPO | Filing, Examination, Granting | 14140 | |
| Japan | Filing, Examination, Granting | 2315 | |
| South Korea | Filing, Examination, Granting | 2449 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
25,510
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
A field-programmable gate array (FPGA) cluster, comprising a plurality of FPGA devices, can be used to accelerate homomorphic encryption functionality. In particular, the FPGA cluster can accelerate the relinearization process used in homomorphic encryption by using multiple FPGA devices to perform portions of the relinearization process in parallel. Further, the use of the FPGA cluster provides sufficient memory resources to allow data used by the relinearization process, namely the keyswitch keys, to be stored on-chip.[French]
L'invention concerne une grappe de réseaux prédiffusés programmables par l'utilisateur (FPGA), comprenant une pluralité de dispositifs FPGA, qui peut être utilisée pour accélérer la fonctionnalité de cryptage homomorphe. En particulier, la grappe de FPGA peut accélérer le processus de relinéarisation utilisé dans un cryptage homomorphe en utilisant de multiples dispositifs FPGA pour effectuer des portions du processus de relinéarisation en parallèle. De plus, l'utilisation de la grappe de FPGA fournit des ressources de mémoire suffisantes pour permettre à des données utilisées par le processus de relinéarisation, à savoir les clés de commutateur de clé, d'être stockées sur puce.