WO2023025321 - SYSTEMS AND METHODS FOR EXECUTING FORWARD ERROR CORRECTION CODING
National phase entry is expected:
Publication Number
WO/2023/025321
Publication Date
02.03.2023
International Application No.
PCT/CN2022/115483
International Filing Date
29.08.2022
Title **
[English]
SYSTEMS AND METHODS FOR EXECUTING FORWARD ERROR CORRECTION CODING
[French]
SYSTÈMES ET PROCÉDÉS D'EXÉCUTION DE CODAGE DE CORRECTION D'ERREURS SANS CIRCUIT DE RETOUR
Applicants **
HUAWEI TECHNOLOGIES CO., LTD.
Inventors
KARIMI, Bashirreza
BARAKATAIN, Masoud
HASHEMI TOROGHI, Yoones
SUKMADJI, Alvin
PAN, Chunpo
Priority Data
63/237,721
27.08.2021
US
Application details
| Total Number of Claims/PCT | * |
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| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
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International Searching Authority |
CNIPA
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| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
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| Type of Assignment |
The Standard Agent's Assignment
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| Applicant's Legal Status |
Legal Entity
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| * | |
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| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1831 | |
| EPO | Filing, Examination, Granting | 13319 | |
| Japan | Filing, Examination, Granting | 2293 | |
| South Korea | Filing, Examination, Granting | 2256 | |
| USA | Filing, Examination, Granting | 5340 |
Total:
25,039
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
Methods and processors for executing Forward Error Correction (FEC) coding are provided. The method includes acquiring a stream of real data symbols from a communication medium. The stream of real data symbols being arranged in a real matrix. The method includes generating virtual data symbols being arranged in a virtual matrix. The generating includes applying an interleaver map onto the matrix such that at most c number of virtual data symbols in a given virtual row of the virtual matrix are copies of real data symbols associated with a same real row of the real matrix, c being a positive integer higher than 1. The method includes decoding codewords formed by the virtual matrix and the real matrix.[French]
L'invention concerne des procédés et des processeurs permettant d'exécuter un codage de correction d'erreurs sans circuit de retour (FEC). Le procédé consiste à acquérir un flux de symboles de données réels à partir d'un support de communication. Le flux de symboles de données réels est disposé dans une matrice réelle. Le procédé consiste à générer des symboles de données virtuels qui sont disposés dans une matrice virtuelle. La génération consiste à appliquer une carte d'entrelaceur sur la matrice de telle sorte qu'au plus c nombres de symboles de données virtuels dans une rangée virtuelle donnée de la matrice virtuelle sont des copies de symboles de données réels associés à une même rangée réelle de la matrice réelle, c étant un nombre entier positif supérieur à 1. Le procédé comprend le décodage de mots de code formés par la matrice virtuelle et la matrice réelle.