WO2023230835 - SCAN CIRCUIT, DISPLAY SUBSTRATE, AND DISPLAY APPARATUS
National phase entry:
Publication Number
WO/2023/230835
Publication Date
07.12.2023
International Application No.
PCT/CN2022/096221
International Filing Date
31.05.2022
Title **
[English]
SCAN CIRCUIT, DISPLAY SUBSTRATE, AND DISPLAY APPARATUS
[French]
CIRCUIT DE BALAYAGE, SUBSTRAT D'AFFICHAGE ET APPAREIL D'AFFICHAGE
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
Inventors
LU, Jiangnan
SHAN, Zhenzhen
ZHU, Jianchao
SHANG, Guangliang
YAO, Xing
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
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| Number of Office Actions | * |
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International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
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| Patent Delivery |
Send the Letters Patent by Courier
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| Translation |
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* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1973 | |
| EPO | Filing, Examination, Granting | 14848 | |
| Japan | Filing, Examination, Granting | 2325 | |
| South Korea | Filing, Examination, Granting | 2361 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
26,247
The term for entry into the National Phase has expired. This quotation is for informational purposes only
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Abstract[English]
A scan circuit having a plurality of stages is provided. A respective stage includes a respective scan unit configured to provide a control signal to at least a row of subpixels. The respective scan unit includes an input subcircuit (Isc) configured to receive a start signal (STV) or an output signal (G_(n-1)) from a previous scan unit, a first processing subcircuit (Psc1), a second processing subcircuit (Psc2), and an output subcircuit (Osc). The output subcircuit (Osc) includes a first output transistor (To1). The input subcircuit (Isc) includes a first input transistor (Ti1) and a second input transistor (Ti2) sequentially coupled between an input terminal (TMi) and a first node (N1). The first node (N1) is coupled to a gate electrode of the first output transistor (To1). The first processing subcircuit (Psc1) includes a first switch transistor (Ts1) and a second switch transistor (Ts2) coupled between the first node (N1) and a first reference terminal (TMr1). The first reference terminal (TMr1) is configured to receive a first reference signal (VREF1).[French]
L'invention concerne un circuit de balayage comportant une pluralité d'étages. Un étage respectif comprend une unité de balayage respective conçue pour fournir un signal de commande à au moins une rangée de sous-pixels. L'unité de balayage respective comprend un sous-circuit d'entrée (Isc) conçu pour recevoir un signal de démarrage (STV) ou un signal de sortie (G_(n-1)) en provenance d'une unité de balayage précédente, un premier sous-circuit de traitement (Psc1), un second sous-circuit de traitement (Psc2) et un sous-circuit de sortie (Osc). Le sous-circuit de sortie (Osc) comprend un premier transistor de sortie (To1). Le sous-circuit d'entrée (Isc) comprend un premier transistor d'entrée (Ti1) et un second transistor d'entrée (Ti2) qui sont successivement couplés entre une borne d'entrée (TMi) et un premier nœud (N1). Le premier nœud (N1) est couplé à une électrode de grille du premier transistor de sortie (To1). Le premier sous-circuit de traitement (Psc1) comprend un premier transistor de commutation (Ts1) et un second transistor de commutation (Ts2) qui sont couplés entre le premier nœud (N1) et une première borne de référence (TMr1). La première borne de référence (TMr1) est conçue pour recevoir un premier signal de référence (VREF1).