WO2023197202 - SEMICONDUCTOR STRUCTURE FOR GATE ALL AROUND NANOSHEET DEVICE
National phase entry:
Publication Number
WO/2023/197202
Publication Date
19.10.2023
International Application No.
PCT/CN2022/086579
International Filing Date
13.04.2022
Title **
[English]
SEMICONDUCTOR STRUCTURE FOR GATE ALL AROUND NANOSHEET DEVICE
[French]
STRUCTURE SEMI-CONDUCTRICE POUR GRILLE TOUT AUTOUR D'UN DISPOSITIF À NANOFEUILLE
Applicants **
HUAWEI TECHNOLOGIES CO.,LTD.
Inventors
BHUWALKA, Krishna Kumar
CHEN, Yijian
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| Number of Office Actions | * |
| * | |
International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
|
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 1646 | |
| EPO | Filing, Examination, Granting | 11721 | |
| Japan | Filing, Examination, Granting | 2196 | |
| South Korea | Filing, Examination, Granting | 1996 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
22,299
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Abstract[English]
For GAA nanosheet devices, a semiconductor structure (100) and fabrication method is provided. The semiconductor structure (100) comprises a substrate (101), a gate stack on the substrate (101) with a plurality of gate regions (103) and silicon-based channel regions (102) alternatingly arranged one on the other. A length of the gate regions (103) is smaller than a length of the channel regions (102). Thus, pockets (104) are formed on a side of the gate stack, each pocket (104) being arranged next to one gate region (103) and between the two channel regions (102) adjacent to the gate region (103). Further, a silicon-based first contact region (105) extends in a distance to the side of the gate stack, and a silicon-based filler material (106) is arranged between the first contact region (105) and the first side of the gate stack and in each first pocket (104).[French]
La présente invention concerne, pour des dispositifs nanofeuilles GAA, une structure semi-conductrice (100) et un procédé de fabrication. La structure semi-conductrice (100) comprend un substrat (101), un empilement de grille sur le substrat (101) avec une pluralité de régions de grille (103) et des régions de canal à base de silicium (102) disposées en alternance l'une sur l'autre. Une longueur des régions de grille (103) est inférieure à une longueur des régions de canal (102). Ainsi, des poches (104) sont formées sur un côté de l'empilement de grille, chaque poche (104) étant disposée à côté d'une région de grille (103) et entre les deux régions de canal (102) adjacentes à la région de grille (103). En outre, une première région de contact à base de silicium (105) s'étend à une certaine distance du côté de l'empilement de grille, et un matériau de charge à base de silicium (106) est disposé entre la première région de contact (105) et le premier côté de l'empilement de grille et dans chaque première poche (104).