WO2023039842 - ARRAY SUBSTRATE AND DISPLAY APPARATUS
National phase entry:
Publication Number
WO/2023/039842
Publication Date
23.03.2023
International Application No.
PCT/CN2021/119097
International Filing Date
17.09.2021
Title **
[English]
ARRAY SUBSTRATE AND DISPLAY APPARATUS
[French]
SUBSTRAT MATRICIEL ET APPAREIL D'AFFICHAGE
Applicants **
BOE TECHNOLOGY GROUP CO., LTD.
CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
Inventors
SHANG, Tinghua
LIU, Biao
WANG, Siyu
CHU, Yuge
ZHANG, Yi
Application details
| Total Number of Claims/PCT | * |
| Number of Independent Claims | * |
| Number of Priorities | * |
| Number of Multi-Dependent Claims | * |
| Number of Drawings | * |
| Pages for Publication | * |
| Number of Pages with Drawings | * |
| Pages of Specification | * |
| * | |
| Number of Office Actions | * |
| * | |
International Searching Authority |
CNIPA
* |
| Recordal of a Change of the Applicant's Name/Address |
Change of Applicant's Name and Address
* |
| Type of Assignment |
The Standard Agent's Assignment
* |
| Applicant's Legal Status |
Legal Entity
* |
| * | |
| * | |
| * | |
| * | |
| * | |
| Entry into National Phase under |
Chapter I
* |
| Patent Delivery |
Send the Letters Patent by Courier
* |
| Translation |
|
* The data is based on automatic recognition. Please verify and amend if necessary.
** IP-Coster compiles data from publicly available sources. If this data includes your personal information, you can contact us to request its removal.
Quotation for National Phase entry
| Country | Stages | Total | |
|---|---|---|---|
| China | Filing, Examination, Granting | 2068 | |
| EPO | Filing, Examination, Granting | 14967 | |
| Japan | Filing, Examination, Granting | 2419 | |
| South Korea | Filing, Examination, Granting | 2494 | |
| USA | Filing, Examination, Granting | 4740 |
Total:
26,688
The term for entry into the National Phase has expired. This quotation is for informational purposes only
Contact Us
Abstract[English]
An array substrate is provided. The array substrate includes K number of reset signal lines respectively configured to provide reset signals to reset transistors in K columns pixel driving circuits of the array substrate. The K number of reset signal lines includes a plurality of third reset signal lines in (2k-1) -th columns of K columns, K and k being positive integers, 1 ≤ k ≤ (K/2); and a plurality of fourth reset signal lines in (2k) -th columns of the K columns. A respective third reset signal line and a respective fourth reset signal line have different line patterns.[French]
L'invention concerne un substrat matriciel. Le substrat matriciel comprend un nombre K de lignes de signal de réinitialisation qui sont respectivement conçues pour fournir des signaux de réinitialisation à des transistors de réinitialisation dans K colonnes de circuit d'attaque de pixels du substrat matriciel. Le nombre K de lignes de signal de réinitialisation comprend une pluralité de troisièmes lignes de signal de réinitialisation dans des (2k-1)-ième colonnes de K colonnes, K et k étant des nombres entiers positifs, et 1 ≤ k ≤ (K/2) ; et une pluralité de quatrièmes lignes de signal de réinitialisation dans des (2k)-ième colonnes des K colonnes. Une troisième ligne de signal de réinitialisation respective et une quatrième ligne de signal de réinitialisation respective ont des motifs de ligne différents.